A Model for Predicting Utilization of Multiple Pipelines in Mtmp Architecture

The conventional single-threaded multiple-pipelined processor is not capable of using multiple pipelines efficiently, and so the processor performance suffers. This paper investigates a multiple-threaded multiple-pipelined (MTMP) processor architecture that tries to issue multiple instructions from multiple instruction threads in every clock cycle. For the performance evaluation, the paper proposes a modified analytic model that provides a quick prediction of utilization of pipelines. Unlike previous analytic models of multiple-threaded architecture, the model presented here concerns the utilization of multiple pipelines. It deals not only with pipeline dependencies but also with structure conflicts. The model can be used for turning processor parameters when a MTMP is designed.